The present invention relates generally to digital time division multiplex systems and, more particularly, to a digital time division multiplex system useful for branching signals from one station to a plurality of stations and a method of controlling such a system.
FIG. 10 shows a conventional time division multiplexer (TDM) consisting of a multiplex control unit 100 for controlling the multiplexing of input signals from data terminal equipment (DTE), an address control memory (ACM) 104 for controlling the addresses of time slots assigned to the input signals, a line interface unit 105 for interfacing with a high-speed digital line by effecting frame formatting, frame synchronizing signal separation, synchronization establishment, and NRZ/CMI code conversion, an address bus 106 for transmitting the address signals output from the ACM 104, a sending bus 107 for transmitting the data to be sent out, a receiving bus 108 for transmitting the received data, and data terminal interface units (DTIF) 111-1 through 111-n one for each DTE.
The DTIFs 111-1 through 111-n are identical and, therefore, only the DTIF 111-1 will be described in detail. The DTIF 111-1 consists of an address decoder (AdDECOD) 112-1 for providing an output when an address signal for each time slot on the address bus 106 matches its own address, a send gate (SGATE) 113-1 and a receive gate (RGATE) 114-1, each responsive to an output from the AdDECOD 112-1 to open, a sending speed converter (SSCONV) 115-1 for converting the speed or bit rate of data from the DTE into that of the high-speed digital line, a receiving speed converter (RSCONV) 116-1 for receiving a predetermined bit group of the data received from the receiving bus 108 when the RGATE 114-1 opens and converting its bit rate into the DTE bit rate, a sending data receiving interface unit (SDRIF) 121-1 for receiving the sending date (SD) to be transmitted, etc. from the DTE, a received data sending interface unit (RDSIF) 122-1 for sending the received data (RD), etc. to the DTE. The SDRIF 121-1 and RDSIF 122-1 may be made according to the standard specifications for the V or X series.
In operation, data signals (SD, etc.) from the DTE are sequentially input to the SDRIF 121-1 in the DTIF 111-1 and then to the SSCONV 115-1 where the speed is converted to that of a high-speed digital line such as 768 Kb/s. The time slot address signals from the ACM 104 are supplied on the address bus 106 so that each of the DTIFs 111-1 through 111-n may receive them. When the address signal matches its own address, the DTIF 111-1 opens the SGATE 113-1 and the RGATE 114-1. At this point, the sending data from the SSCONV 115-1 is put on the sending bus 107 through the SGATE 113-1. The sending data on the sending bus 107 is input to the line interface unit 105 where it is converted into NRZ/CMI codes and put into a predetermined time slot or bit position of a transmission frame on the high-speed digital line. All the outputs from the DTIFs 111-1 through 111-n are sequentially put into the time slots on the sending bus 107 according to the address contents stored in the ACM 104.
On the other hand, the signals received from the high-speed digital line is converted into CMI/NRZ codes in the line interface unit 105, and the frame synchronization is separated and the synchronization is established. The received data is then put on the receiving bus 108 at the same bit rate as that of the high-speed digital line. Since the time slot of the received data and the output of the ACM 104 are synchronized, when the AdDECODE 112-1 finds its own address, the DTIF 111-1 opens RGATE 114-4 to read the received data in the time slot from the receiving bus 108 and input it to the RSCONV 116-1. The output is input to the RDIF 122-1 where it is converted into the data signal (RD, etc.) of the same bit rate as that of the DTE and output to the DTE.
Such a conventional TDM system is able to provide point-to-point services but unable to adapt itself to recent branching services. A conventional bidirectional branching system for providing branching services, and the signals to be transmitted will be described.
FIG.11 shows a bidirectional branching unit (BU) 5 consisting of a pair of A directional lines 51 and 52, a pair of B directional lines 53 and 54, a pair of C directional lines 55 and 56, three input terminals IN-A through IN-C, three output terminals OUT-A through OUT-C, and three AND gates 57, 58, and 59. The data input at the IN-A 51 is output at the OUT-B 54 when the IN-C 55 is a logical "1" but becomes a logical "0" when the IN-C 55 is a logical "0". When an all "1" code for the channel is input at the IN-C 55, the data input at the IN-A 51 is output at the OUT-B 54 as it is. At the same time, the data input at the IN-A 51 is output at the OUT-C 56 when the IN-B 53 is a logical "1" but becomes a logical "0" when the IN-B 53 is a logical "0". When an all "1" code for the channel is input at the IN-B 53, the data input at the IN-A 51 is output at the OUT-C 56 as it is.
FIG. 12 illustrates how signals are transmitted in an exemplary system which consists of four stations M1 through M4, each having a TDM, connected via high-speed digital lines in which a couple of BUs 5 and 6 are installed. Six channels (4Cz=6) are provided to transmit signals among the stations M1 through M4. It can be seen that data A through L and an all "1" code are assigned to respective channels. That is to say, data A is assigned to a sending channel CH1 in the station M1 (TDM1) and is received by the station M2 (TDM2). Similarly, data B is assigned to the sending channel CH2 and received by the station M3 (TDM3). Similarly, data C is assigned to a sending channel CH3 and received by the station M4 (TDM4).
All "1" for setting all bits in the channel to "1" is assigned to channels CH4 through CH6 for transmission. The signal sent by the TDM1 is input to the IN-A 51 of the BU 5 and output at the OUT-B 54 via the AND gate 57 and at the OUT-C 56 via the AND gate 59. By means of the BU 5, the data A AND G, B, C, D, E, and all "1" are output in the channels CH1, CH2, CH3, CH4, CH5, and CH6 of the OUT-B 54, respectively, while the data A, B AND H, C AND I, J, K, and F AND L are output in the channels CH1, CH2, CH3, CH4, CH5, and CH6 of the OUT-C 56, respectively. The signals received in the CH1, CH4, and CH5 of the TDM2 of the station M2 are single data and correct, but the signals in the CH2, CH3, and CH6 are not correct data and neglected when received. In this way, communication is carried out among the respective stations.
FIG. 13 shows an example of the bit settings of the sending control signals 109 and the receiving control signals 110 to be transmitted over the digital line. The columns represent the stations M1 through M4 each having a TDM installed and the rows represent channel bit group Nos. of the sending control signal 109 and the receiving control signal 110.
FIGS. 14a and 14b illustrate a signal frame format and a 20-frame multiframe format, respectively. The bit rate of a digital line in the signal frame in FIG. 14a is 1.536 Mb/s so that the bit length of a frame available to users is 192 bits, in which the bit Nos. 1, 2, and 3-192 are used as a multiframe synchronizing bit (MF) and a service channel bit (SC) for sending a service signal, and data bits for sending data, respectively. The transmission speed of a bit of information in the multiframe of FIG. 14b is 400 b/s so that by using appropriate bits, it is possible to multiplex low-speed data into high-speed data for transmission.
In the conventional bit multiplex TDM, voice or data is put on the bit Nos. 2-192 of a signal frame for transmission. However, in the FIG. 14a example, the bit No. 2 is used as a service channel (SC) for transmitting information among stations. Since the transmission speed of a bit of information is 8 Kb/s, the transmission speeds of 64 Kb/s and 32 Kb/s require 8 and 4 bits, respectively. For transmission speeds lower than these, the multiframe is utilized.
Since the transmission speed of a bit of information in the multiframe is 400 b/s, data of 1.2 Kb/s is transmitted in three frames of the same bit number. For example, the data is assigned to the bit No. 5 and transmitted in the three frames MFR Nos. 1-3. Data of 2.4 Kb/s is transmitted in six frames of the same bit number. For example, the data is assigned to the bit No. 6 and transmitted in the MFR Nos. 1-6. Data of 9.6 Kb/s is transmitted in 24 frames of the same bit number. For example, the data is assigned to bit Nos. 7 and 8 and transmitted in the MFR Nos. 1-20 for the bit No. 7 and the MFR Nos. 1-4 for the bit No. 8.
Both high-speed and low-speed data may be assigned in a single frame. For example, low-speed data is assigned to the leading half of a frame and high-speed data is assigned to the tailing half of the frame.